A memory device is developed to increase the memory capacity, in which a memory cell array is disposed above a circuit. A NAND memory device in which memory cells are arranged three-dimensionally includes, for example, a plate-shaped conductive layer provided above a circuit, multiple electrode layers stacked above the conductive layer, and semiconductor pillars extending through the multiple electrode layers. In such a memory device, there is a demand for manufacturing technology capable of stably forming holes with high aspect ratio to provide the semiconductor pillars therein.